Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback

We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block the issuing of new instructions. The design has been optimized for low-power operation and has not been constrained by the formal verification effort. Additional improvements for the implementation were identified through formal verification. The formal verification of the design also incorporates the implementation of clock-gating and control logic. The core of the verification effort was based on ACL2 theorem proving. Additionally, model checking has been used to verify some properties of the floating-point scheduler that are relevant for the correct operation of the unit.Comment: In Proceedings ACL2 2011, arXiv:1110.447

Modeling Algorithms in SystemC and ACL2

We describe the formal language MASC, based on a subset of SystemC and intended for modeling algorithms to be implemented in hardware. By means of a special-purpose parser, an algorithm coded in SystemC is converted to a MASC model for the purpose of documentation, which in turn is translated to ACL2 for formal verification. The parser also generates a SystemC variant that is suitable as input to a high-level synthesis tool. As an illustration of this methodology, we describe a proof of correctness of a simple 32-bit radix-4 multiplier.Comment: In Proceedings ACL2 2014, arXiv:1406.123

A Formalization of Finite Group Theory: Part II

This is the second installment of an exposition of an ACL2 formalization of finite group theory. The first, which was presented at the 2022 ACL2 workshop, covered groups and subgroups, cosets, normal subgroups, and quotient groups, culminating in a proof of Cauchy's Theorem: If the order of a group G is divisible by a prime p, then G has an element of order p. This sequel addresses homomorphisms, direct products, and the Fundamental Theorem of Finite Abelian Groups: Every finite abelian group is isomorphic to the direct product of a list of cyclic p-groups, the orders of which are unique up to permutation. This theorem is a suitable application of ACL2 because of its extensive reliance on recursion and induction as well as the constructive nature of the factorization. The proof of uniqueness is especially challenging, requiring the formalization of vague intuition that is commonly taken as self-evident.Comment: In Proceedings ACL2-2023, arXiv:2311.0837

A Formalization of Finite Group Theory: Part III

This is the third and final installment of an exposition of an ACL2 formalization of finite group theory. Part I covers groups and subgroups, cosets, normal subgroups, and quotient groups. Part II extends the theory in the developmnent of group homomorphisms and direct products, which are applied in a proof of the Fundamental Theorem of Finite Abelian Groups. The central topics of the present paper are the symmetric groups and the Sylow theorems, which pertain to subgroups of prime power order. Since these theorems are based on the conjugation of subgroups, an example of a group action on a set, their presentation is preceded by a comprehensive treatment of group actions. Our final result is mainly an application of the Sylow theorems: after showing that the alternating group of order 60 is simple (i.e., has no proper normal subgroup), we prove that no group of non-prime order less than 60 is simple. The combined content of the groups directory is a close approximation to that of an advanced undergraduate course taught by the author in 1976.Comment: In Proceedings ACL2-2023, arXiv:2311.0837

A formal language for the specification and verification of synchronous and asynchronous circuits

A formal hardware description language for the intended application of verifiable asynchronous communication is described. The language is developed within the logical framework of the Nqthm system of Boyer and Moore and is based on the event-driven behavioral model of VHDL, including the basic VHDL signal propagation mechanisms, the notion of simulation deltas, and the VHDL simulation cycle. A core subset of the language corresponds closely with a subset of VHDL and is adequate for the realistic gate-level modeling of both combinational and sequential circuits. Various extensions to this subset provide means for convenient expression of behavioral circuit specifications

A Mechanical Proof of the Chinese Remainder Theorem

r i m i + s i M i = 1. Thus, s i M i = 1 \Gamma r i m i j 1 (mod m i ) and for each j 6= i, s i M i j 0 (mod m j ): Let x = P k i=1 a i s i M i . Then for i = 1; : : : ; k, x = a i s i M i + k X j=1 j 6=i a i s i M i j a i \Delta 1 + 0 j a i (mod m i ):2 1 Alth

A Verified Prolog Compiler for the Warren Abstract Machine

Machine David M. Russinoff Microelectronics and Computer Technology Corporation 3500 West Balcones Center Drive Austin, TX 78759 (512) 338-3583 Abstract We extend the theory of Prolog to provide a framework for the study of Prolog compilation technology. For this purpose, we first demonstrate the semantic equivalence of two Prolog interpreters: a conventional SLD-refutation procedure and one that employs Warren's "last call" optimization. Next, we formally define the Warren Abstract Machine (WAM) and its instruction set and present a Prolog compiler for the WAM. Finally, we prove that the WAM execution of a compiled Prolog program produces the same result as the interpretation of its source. Contents 1 Introduction 1 2 Prolog 4 2.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Last Call Optimization . . . . . . . . . . . . . . . . . . . . . . 10 3 The WAM 15 3.1 WAM States . ..